The present invention relates to a control circuit for controlling an output voltage of a DC--DC converter. More particularly, the present invention relates to a control circuit for use with a DC--DC converter which supplies operational power to various types of semiconductor integrated circuit (IC) devices, such as a central processing unit (CPU) and a memory (RAM, ROM, etc.), mounted on any of various types of electronic apparatuses.
In portable electronic equipment which operates on power from a battery serving as a power source, if an internal circuit must be supplied with a DC voltage differing from the voltage of the battery, the desired DC voltage is produced by a DC--DC converter which operates on power from a battery power source. If a plurality of source voltages are used, there is a risk of damaging a device if a sequence of turn-on and shutdown of the power sources is not taken account. Accordingly, there is a need to control the rising and falling forms of an output voltage from the DC--DC converter.
FIG. 1 shows an example of a conventional DC--DC converter used as a power supply circuit of semiconductor integrated circuit devices, such as a CPU or a microcomputer. The DC--DC converter 101 comprises a control circuit 102 formed on a single integrated circuit chip, and a plurality of external elements. The control circuit 102 receives a control signal CTL and is activated when the control signal CTL is high.
A first output signal OUT1 of the control circuit 102 is input to the gate of an output transistor 103, and the drain of the output transistor 103 is connected to a power source Vcc. The output transistor 103 is an N-channel MOS transistor.
The source of the output transistor 103 is connected to the drain of a synchronous rectifying transistor 104, and a second output signal OUT2 from the control circuit 102 is input to the gate of the synchronous rectifying transistor 104 whose source is connected to a ground GND. The synchronous rectifying transistor 104 is also an N-channel MOS transistor.
The source of the output transistor 103 is connected to an output terminal To via an output coil 105. The source of the output transistor 103 is also connected to the cathode of a fly-wheel diode 106 whose anode is connected to the ground GND. The output terminal To is connected to the ground GND via a capacitor 107.
In the DC--DC converter 101, the first and second output signals OUT1 and OUT2 are output from the control circuit 102 when the control circuit 102 is activated. The first and second output signals OUT1 and OUT2 are output in the form of complementary pulse signals. Accordingly, the output transistor 103 and the synchronous rectifying transistor 104 are alternately turned on.
An electric current output from the output transistor 103 is smoothed by means of the output coil 105 and the capacitor 107 through switching operation of the output transistor 103. When the output transistor 103 is turned off, an output voltage Vo output from the output terminal To is smoothed by means of the electrical current supplied to the output coil 105 via the flywheel diode 106 from the capacitor 107. Further, the synchronous rectifying transistor 104 is turned on by the second output signal OUT2, so that a forward voltage drop of the flywheel diode 106 is reduced to substantially zero, thereby improving smoothing efficiency.
At this time, the synchronous rectifying transistor 104 is turned on, after the output transistor 103 has been turned off, and is turned off before the output transistor 103 is turned back on. Therefore, a through current is prevented from flowing from the power source Vcc to the ground GND via the output transistor 103 and the synchronous rectifying transistor 104.
Through the foregoing operations, a DC output voltage Vo is output from the output terminal To, and the voltage level of the output voltage Vo is maintained constant by adjustment of the duty factor of each of the first and second output signals OUT1 and OUT2.
If the control signal CTL goes low, deactivating the control circuit 102 while the output transistor 103 is performing a switching operation, the output transistor 103 and the synchronous rectifying transistor 104 are held in an off state.
The electric charge stored in the capacitor 107 is discharged via a load connected to the output terminal To. As a result, as shown in FIG. 2, the output voltage Vo is reduced to low (ground GND).
At this time, the time required for the output voltage Vo to decrease to low differs according to the value of the discharge current flowing into the load and the time constant defined by the capacitance of the capacitor 107. Accordingly, the time required for the output voltage Vo to decrease to low is dependent on the load connected to the output terminal To.
Under these circumstances, the time required to stop the supply of power to the load in response to the trailing edge of the control signal CTL becomes unstable. For this reason, in the semiconductor integrated circuit device that operates on a plurality of source voltages, there arises a risk of erroneous operations of a CPU, or the like, connected to the power supply circuit as a load.
As indicated by a dotted line in FIG. 1, an N-channel MOS transistor, which is turned on when the control signal CTL goes low, is connected as a discharge transistor 108 between the output terminal To and the ground GND. The current drive capability of the discharge transistor 108 is set to be sufficiently greater than the discharge current drive capability of the load.
With the foregoing configuration, the rate at which the output voltage Vo decreases, in response to the reduction of the voltage level of the control signal CTL, to low level is substantially constant, as determined by the time constant of the capacitance 107 and the discharge transistor 108, regardless of the load.
The foregoing configuration, however, requires addition of the discharge transistor 108 having a large current drive capability, thereby increasing the cost and the size of the DC--DC converter.
If the DC--DC converter is configured such that the synchronous rectifying transistor 104 is turned on when the control signal CTL goes low, there is no need to add the discharge transistor 108 to the DC--DC converter.
However, such a configuration requires addition to the control circuit 102 of a circuit for turning on the synchronous rectifying transistor 104 when the control signal CTL goes low. Accordingly, the chip area of the semiconductor device equipped with the control circuit 102 is increased, thereby hindering a reduction in the size of the DC--DC converter.
A plurality of semiconductor integrated circuit devices (ICs) are mounted on an electronic apparatus. These semiconductor integrated circuit devices individually require operational power. In general, the operational power is provided by a DC--DC converter. If there is a failure to provide the ICs with stable power supply or to execute a power-up sequence of the ICs, the ICs cause faulty operation. For this reason, there is a demand for highly accurate power-up operation.
A DC power produced by conversion of a commercial power by means of a power supply circuit (an AC-DC converter) is commonly used as the power source for various types of electronic equipment. The thus-converted DC power is further converted into operational power corresponding to each of the ICs by means of the DC--DC converter 101. The thus-converted operational power is supplied to the corresponding IC. Referring to FIG. 5, an electronic device 300 includes semiconductor integrated circuit devices 301, such as a central processing unit (CPU), a chip selector, and a memory (RAM or ROM); a power supply circuit 302; and a DC--DC converter 201. The power supply circuit 302 converts a commercial power VA into various types of DC power Vcc and Vin. The DC--DC converter 201 regulates the thus-converted DC voltage Vin to obtain stable operational power (i.e., an output voltage Vout) and supplies the thus-obtained operational power to each of the semiconductor integrated circuit devices 301.
FIG. 3 is a circuit diagram of the DC--DC converter 201. The DC--DC converter 201 comprises a control circuit 202 formed on a one-chip semiconductor integrated circuit device, and a plurality of external elements. A signal SG1 output from the control circuit 202 is supplied to the gate of an output transistor 203 composed of an enhanced N-channel MOS transistor. A DC supply voltage Vin is supplied to the drain of the output transistor 203 from the power supply circuit 302 shown in FIG. 5, and the source of the output transistor 203 is connected to an output terminal 205 via an output coil 204. The output terminal 205 is also connected to each of the semiconductor integrated circuit devices 301 which serve as loads.
The source of the output transistor 203 is connected to the cathode of the flywheel diode 206 composed of a Schottky diode. The anode of the flywheel diode 206 is connected to the ground GND. A junction between the output coil 204 and the output terminal 205 is connected to the ground GND via a capacitor 207, and a smoothing circuit is formed from a combination of the output coil 204 and the capacitor 207. The junction between the output coil 204 and the output terminal 205 is connected to the control circuit 202 via a resistor 208, such that the output voltage Vout is provided to the control circuit 202.
The control circuit 202 comprises a reference voltage generation circuit 211; an initial malfunction prevention circuit 212; a triangular wave oscillation circuit 213; a dead time circuit 214; an error amplification circuit 215; a constant current circuit 216; a PWM comparison circuit 217; an output circuit 218; and first and second transistors 219, 220.
A drive source voltage Vcc is supplied to the reference voltage generation circuit 211 from the power supply circuit 302, and the reference voltage generation circuit 211 receives a control signal SG2 from an unillustrated external device via an external control input terminal 221. The reference voltage generation circuit 211 is composed of a band-gap reference circuit and generates a reference voltage Vref (&lt;Vcc) from the drive source voltage Vcc as a first reference voltage in response to the control signal SG2 being high. As shown in FIG. 4, if the control signal SG2 goes high at time t0, the reference voltage Vref rises at a given rate and reaches a specified voltage Vref1 (&lt;Vcc). Subsequently, the reference voltage Vref is maintained at the specified voltage Vref1.
The initial malfunction prevention circuit 212 receives the drive source voltage Vcc from the power supply circuit 302 and the reference voltage Vref as a bias voltage from the reference voltage generation circuit 211. The initial malfunction prevention circuit 212 is designed to output a cancel signal SG3 which goes from high to low when the reference voltage Vref which is in the course of rising to the specified voltage Vref1 reaches a given voltage Vref2, as shown in FIG. 4; i.e., at time t1, at which time the reference voltage Vref reaches the bias voltage (=Vref2), which permits operation of the initial malfunction prevention circuit 212.
The triangular wave oscillation circuit 213 receives the drive source voltage Vcc from the power supply circuit 302 and the reference voltage Vref as the bias voltage from the reference voltage generation circuit 211. When the reference voltage Vref increases to a given voltage Vref3 (&gt;Vref2) as shown in FIG. 4, the triangular wave oscillation circuit 213 commences at a point in time between time t1 and time t2, at which time the reference voltage Vref reaches the bias voltage (=Vref3), which permits oscillation of the triangular wave oscillation circuit 213, thereby outputting a triangular wave signal SG4 which oscillates within a given voltage range.
The dead time circuit 214 is composed of a potential dividing circuit including a plurality of resistors connected in series and receives the reference voltage Vref from the reference voltage generation circuit 211 and divides it. The thus-divided voltage is output as a limit signal SG5. As shown in FIG. 4, if the control signal SG2 goes high at time t0, the limit signal SG5 rises at a given rate, as does the reference voltage Vref. The limit signal SG5 reaches a rated or predetermined voltage Vk (&lt;Vref1) at time t2 and is maintained at the rated voltage Vk thereafter. The rated voltage Vk of the limit signal SG5 is set to a value slightly lower than the maximum value of the triangular wave signal SG4 by control of the voltage-dividing ratio of the resistors in the dead time circuit 214. More specifically, the rated voltage Vk is set to a value such that the duty ratio of a pulse signal of an output signal SG1 from the output circuit 218 becomes 90% when the triangular wave signal SG4 is compared with the limit signal SG5 by means of the PWM comparison circuit 217.
The error amplification circuit 215 has an inverting input terminal, which serves as an input terminal for receiving a detected voltage, and first and second noninverting input terminals, which serve as first and second reference voltage input terminals. The inverting input terminal receives the output voltage Vout via the resistor 208. The error amplification circuit 215 receives the drive source voltage Vcc from the power supply circuit 302 and the reference voltage Vref as the bias voltage from the reference voltage generation circuit 211. The second noninverting input terminal of the error amplification circuit 215 is connected to the ground GND via an external capacitor 222 for gentle start-up purposes. The capacitor 222 receives a constant current from the constant current circuit 216, which operates on the reference voltage Vref received from the reference voltage generation circuit 211. The capacitor 222 is charged by the constant current received from the constant current circuit 216, and the charge voltage Vsof of the constant current increases to the reference voltage Vref. That is, the charge voltage Vsof serves as a second reference voltage with respect to the reference voltage Vref that serves as the first reference voltage. The charge voltage Vsof is produced by the reference voltage generation circuit 211 and the capacitor 222.
The second noninverting input terminal of the error amplification circuit 215 is also connected to the collector of the first transistor 219 for gentle start-up purposes, and the emitter of the first transistor 219 is connected to the ground GND. The base of the first transistor 219 receives the cancel signal SG3 from the initial malfunction prevention circuit 212. Accordingly, if the cancel signal SG3 drops to low from high at time t1 to thereby switch the first transistor 219 from an on state to an off state, the charging of the capacitor 222 with the constant current from the constant current circuit 216 is started. As a result, as shown in FIG. 4, the charge voltage Vsof starts increasing at time t1.
A series circuit comprising an external capacitor 223 and a resistor 224 is connected between an output terminal and the inverting input terminal of the error amplification circuit 215, thereby preventing oscillation of the error amplification circuit 215.
The error amplification circuit 215 compares either the reference voltage Vref or the charge voltage Vsof, whichever voltage is lower, with the output voltage Vout. The error amplification circuit 215 produces an error output signal SG6 by amplification of a difference between the thus-compared voltages and outputs the error output signal SG6 to the PWM comparison circuit 217 in the following stage.
As shown in FIG. 4, the error amplification circuit 215 outputs the output voltage SG6 corresponding to the reference voltage Vref without comparison and amplification until the reference voltage Vref reaches a given voltage; i.e., until time t1, at which time the initial malfunction prevention circuit 212 outputs the cancel signal SG3 low. In other words, since logical inversion occurs when at least one of the first and second noninverting input terminals has a voltage near zero volts, the bias voltage, or the error output signal SG6 having the same amplitude as that of the reference voltage Vref, is output.
After time t1, the error amplification circuit 215 compares the output voltage Vout with either the reference voltage Vref or the charge voltage Vsof, whichever voltage is lower, and amplifies a potential difference between the voltages.
The PWM comparison circuit 217 receives the drive source voltage Vcc from the power supply circuit 302 and has an inverting input terminal and first and second noninverting input terminals. The noninverting input terminal of the PWM comparison circuit 217 receives the triangular wave signal SG4 from the triangular wave oscillation circuit 213. The first noninverting input terminal of the PWM comparison circuit 217 receives an error input signal SG6 from the error amplification circuit 215. The second noninverting input terminal of the PWM comparison circuit 217 receives the limit signal SG5 from the dead time circuit 214.
The PWM comparison circuit 217 compares either the error output signal SG6 or the limit signal SG5, whichever has a lower voltage, with the triangular wave signal SG4. The PWM comparison circuit 217 outputs a pulse signal to the output circuit 218 as a duty control signal SG7, which goes low when the triangular wave signal SG4 has a voltage higher than that of the compared signal, and goes high when the triangular wave signal SG4 has a voltage equal to or smaller than that of the compared signal.
The output terminal of the PWM comparison circuit 217 is connected to the collector of the second transistor 220, and the emitter of the second transistor 220 is connected to the ground GND. The base of the second transistor 220 receives the cancel signal SG3 from the initial malfunction prevention circuit 212. Accordingly, when the cancel signal SG3 decreases to low to thereby turn off the second transistor 220, the duty control signal SG7 is output to the output circuit 218 in the following stage. The output circuit 218 receives the drive source voltage Vcc from the power supply circuit 302. The output circuit 218 outputs to the gate of the transistor 203 the duty control signal SG7 as the above-described output signal SG1.
The DC--DC converter 201 is in a suspended state when the reference voltage generation circuit 211 receives the control signal SG2 low from an external device while the drive source voltage Vcc is supplied to each of the circuits 211-213, 215, 217, and 218 in the control circuit 202 from the power supply circuit 302 shown in FIG. 5.
That is, the reference voltage Vref used for generating a reference voltage is zero volts. Accordingly, a reference voltage Vref of zero volts is supplied to the first noninverting input terminal of the error amplification circuit 215, and the initial error malfunction prevention circuit 212 receives the reference voltage Vref of zero volts. The cancel signal SG3 is high, and therefore the first and second transistors 219 and 220 are in an on state. As a result, the first noninverting input terminal of the error amplification circuit 215 is zero volts. Further, since the second transistor 220 is in an on state, the output signal SG1 goes low. Accordingly, the output transistor 203 is in an off state, and the output voltage Vout is zero volts.
When the control signal SG2 high is supplied to the reference voltage generation circuit 211 from an external device at time t0, the DC--DC converter 201 commences operation. In response to the control signal SG2 high, the reference voltage generation circuit 211 generates the reference voltage Vref on the basis of the drive source voltage Vcc. At this time, as shown in FIG. 4, the reference voltage Vref increases at a given rate to the specified voltage Vref1. The gradually increasing reference voltage Vref is supplied to the initial malfunction prevention circuit 212, the triangular wave oscillation circuit 213, the dead time circuit 214, the noninverting input terminal of the error amplification circuit 215, and the constant current circuit 216.
At this time, although the increasing reference voltage Vref is supplied to the first noninverting input terminal of the error amplification circuit 215, the charge voltage Vsof input to the second noninverting input terminal of the error amplification circuit 215 is zero volts. Therefore, the error output signal SG6 of the error amplification circuit 215 increases in such a way as to have the same magnitude as that of the increasing reference voltage Vref. Further, the dead time circuit 214 supplies to the PWM comparison circuit 217 the limit signal SG5 proportional to the reference voltage Vref.
Consequently, the PWM comparison circuit 217 compares the limit signal SG5 from the dead time circuit 214 with the triangular wave signal SG4 from the triangular wave oscillation circuit 213. At this time, the triangular wave oscillation circuit 213 has not yet commenced oscillation, and hence the triangular wave signal SG4 is zero volts. As a result, the PWM comparison circuit 217 outputs the duty control signal SG7 high. However, since the second transistor 220 is in an on state, the duty control signal SG7 goes low. The output circuit 218 still outputs the signal SG1 low, so that the output transistor 203 is left in an off state.
At time t1, the initial malfunction prevention circuit 212 outputs the cancel signal SG3 low to the base of each of the first and second transistors 219, 220, thereby turning off the first and second transistors 219, 220. When the first transistor 219 is turned off, the capacitor 222 commences accumulation of electric current, and the charge voltage Vsof is supplied to the second noninverting input terminal of the error amplification circuit 215. The charge voltage Vsof is lower than the reference voltage Vref, and hence the error amplification circuit 215 compares the output voltage Vout with the charge voltage Vsof and amplifies a difference between the voltages. The error output signal SG6 is then output to the PWM comparison circuit 217. Immediately after time t1, the output voltage Vout is zero volts, and the charge voltage Vsof is slightly larger than zero volts. Therefore, since the difference between the charge voltage Vsof and the output voltage Vout is small, the error output signal SG6 from the error amplification circuit 215 decreases.
At time t1, the triangular wave oscillation circuit 213 has not yet commenced oscillation. Therefore, the PWM comparison circuit 217 compares the limit signal SG5 with the triangular wave signal SG4 until the error output signal SG6 from the error amplification circuit 215 becomes smaller than the limit signal SG5 from the dead time circuit 214. When the error output signal SG6 becomes smaller than the limit signal SG5, the PWM comparison circuit 217 compares the error output signal SG6 with the triangular wave signal SG4. However, the triangular wave oscillation circuit 213 has not yet commenced oscillation, and the triangular wave signal SG4 is zero volts. As a result, the PWM comparison circuit 217 outputs a duty control signal SG7 high.
At this time, the second transistor 220 is in an off state, and therefore the duty control signal SG7 high is output to the output circuit 218. Accordingly, the signal SG1 output from the output circuit 218 goes high, and the output transistor 203 is turned on. The source voltage Vin is supplied to the output terminal 205 via the output coil 204, and the output voltage Vout increases to the source voltage Vin from zero volts. The thus-increasing output voltage Vout is supplied to the error amplification circuit 215.
The triangular wave oscillation circuit 213 oscillates and outputs the triangular wave SG4. When the triangular wave signal SG4 becomes greater than the error output signal SG6, the duty control signal SG7 of the PWM comparison circuit 217 goes low. The output signal SG1 from the output circuit 218 goes low, and the output transistor 203 is turned off. As a result, the supply of the source voltage Vin to the capacitor 207 is interrupted, so that the capacitor 207 discharges, thereby resulting in a drop in the output voltage Vout.
The error amplification circuit 215 compares the decreasing output voltage Vout with the charge voltage Vsof and outputs the error output signal SG6 to the PWM comparison circuit 217. Since the decreasing output voltage Vout is greater than the charge voltage Vsof, the error output signal SG6 from the error amplification circuit 215 is smaller than the triangular wave signal SG4. Accordingly, the PWM comparison circuit 217 maintains output of the duty control signal SG7 low. More specifically, the output voltage Vout continues decreasing while the output transistor 203 is maintained in an off state.
When the output voltage Vout becomes smaller than the charge voltage Vsof, the voltage of the error output signal SG6 from the error amplification circuit 215 increases and reaches a voltage range corresponding to the oscillation range of the triangular wave signal SG4. When the error output signal SG6 reaches the voltage range corresponding to the oscillation range of the triangular wave signal SG4, the PWM comparison circuit 217 outputs the duty control signal SG7, which goes high when the error output signal SG6 is larger than the triangular wave signal SG4, and goes low when the error output signal SG6 is smaller than the triangular wave signal SG4.
The DC--DC converter 201 controls the output voltage Vout such that it follows the increasing charge voltage Vsof. When the charge voltage Vsof reaches the specified voltage Vref1, the DC--DC converter 201 controls the output voltage Vout such that the output voltage Vout is maintained at the reference voltage Vref; i.e., the specified voltage Vref1.
That is, in an ordinary state, the error amplification circuit 215 compares the reference voltage Vref (predetermined voltage value Vref1) with the output voltage Vout and outputs the error output signal SG6 to the PWM comparison circuit 217. The PMW comparison circuit 217 compares the error output signal SG6 with the triangular wave signal SG4 and outputs the duty control signal SG7 in order to control the output transistor 203 through duty control. Thus, the DC--DC converter 201 is controlled such that the output voltage Vout is maintained at the reference voltage Vref (predetermined voltage value Vref1).
Upon power-up (i.e., upon receipt of the control signal SG2 low), the DC--DC converter 201 performs gentle start-up operation, in which the output voltage Vout is increased, gradually, to the specified voltage Vref1 of the reference voltage Vref. By means of a gentle start-up circuit composed of the first transistor 219, the capacitor 222, the error amplification circuit 215, and the constant current supply circuit 216, the DC--DC converter 201 increases the output voltage Vout to the reference voltage Vref in accordance with an increase in the charge voltage Vsof. In a case where the output voltage Vout is increased to the predetermined voltage specified voltage Vref1 of the reference voltage Vref, the output transistor 203 is kept in an on state. However, by virtue of the gentle start-up circuit, the output transistor 203 is prevented from being held in an on state, which in turn prevents deterioration of the transistor 203.
When the initial malfunction prevention circuit 212 outputs the cancel signal SG3 low at the time of the gentle start-up operation being performed by the DC--DC converter, the duty control signal SG7 immediately goes high irrespective of the charge voltage Vsof, and the output transistor 203 is immediately turned on. In other words, the gentle start-up function becomes temporarily inactive. This is attributable to the fact that the triangular wave oscillation circuit 213 does not oscillate even when the triangular wave oscillation circuit 213 goes low.
The output transistor 203 becomes temporarily turned on before the gentle start-up operation is performed, so that an excess electric current flows to the output transistor 203, thereby deteriorating the output transistor 203.
As a result of the output transistor 203 being abruptly turned on, the output voltage Vout sharply increases and becomes unstable. Such an unstable output voltage Vout is supplied as operational power to each of the semiconductor integrated circuit devices, thereby resulting in fault operations between the semiconductor integrated circuit devices. Particularly, a problem arises in a case where the semiconductor integrated circuit devices 301 are required to be turned on at predetermined timings; i.e., in accordance with a predetermined sequence.
Upon receipt of an uncertain input, the PWM comparison circuit 217 may output the duty control signal SG7 high. In such a case, similar problems arise.
Accordingly, a first object of the present invention is to provide a discharge control circuit which enables control of the trailing edge of an output voltage regardless of a load while reducing the size of a circuit area.
A second object of the present invention is to provide a DC--DC converter control circuit which ensures execution of gentle start-up operation and enables stable supply of an output voltage.